Localized temperature control during rapid thermal anneal

ABSTRACT

Disclosed are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal and, thereby, to selectively control variations in device performance and/or to selectively optimize the anneal temperature of such devices. Selectively controlling the temperature changes in different devices during a rapid thermal anneal is accomplished by selectively varying the isolation material thickness in different sections of a shallow trench isolation structures. Alternatively, it is accomplished by selectively varying the pattern of fill structures in different sections of a semiconductor wafer so that predetermined amounts of shallow trench isolation regions in the different sections are exposed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Division of U.S. application Ser. No. 11/678,799 filed Feb. 26, 2007, the complete disclosure of which, in its entirety, is herein incorporated by reference.

BACKGROUND

1. Field of the Invention

The embodiments of the invention generally relate to semiconductor wafers and, more particularly, to semiconductor wafer structures and methods of forming the structures that optimize variations in reflectance and absorption characteristics.

2. Description of the Related Art

Semiconductor wafer fabrication often involves the use of a rapid thermal anneal (RTA) process to affect the electrical properties of active devices on the wafer. More specifically, an RTA process can be used to activate dopants, diffuse dopants, re-amporphize structures, repair damage from ion implantation processes, etc. RTAs are typically performed by powerful halogen lamp-based heating equipment or lasers which direct radiation onto a wafer surface in order to change the wafer temperature. However, variations in the reflectance and absorption in different regions of a wafer can result in non-uniform temperature changes across the wafer during thermal anneal processes. These non-uniform temperature changes can result in temperature variations on the wafer of 10° C. or more.

Variations in reflectance and absorption characteristics can be caused by a variety of different factors including, different materials, the patterns of those materials in different regions of a wafer and the thicknesses of those materials in different regions of the wafer. For example, dielectric materials (e.g., silicon dioxide (SiO₂)) in shallow trench isolation structures have different reflectance and absorption characteristics than semiconductor materials (e.g., silicon or silicon germanium) incorporated into devices. Dense regions of a wafer (i.e., regions of a wafer having a high number of devices) will have a higher silicon to silicon dioxide ratio than less dense regions. Different silicon-to-silicon dioxide ratios in different regions of the wafer will result in non-uniform temperature changes during a RTA. These non-uniform temperature changes can cause variations in dopant activation, damage repair, etc. across the wafer and can, thereby, cause variations in threshold voltages, sheet resistances, drive currents, leakage currents, etc. between devices on different regions of the wafer. Thus, non-uniform temperature changes can cause significant, location-dependent, variations in device performance.

Furthermore, as technologies continue to scale, anneal ramp times will continue to decrease (e.g., to sub-second ramps) and these faster ramp times will be accompanied by an even greater sensitivity to variations in reflectance and absorption characteristics across a wafer.

SUMMARY

Disclosed herein are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes (i.e., the maximum anneal temperature that will be achieved in different regions) during a single rapid thermal anneal and, thereby, to selectively control variations in device performance (e.g., to form devices with different threshold voltages (Vt) in different regions on the same wafer) and/or to selectively optimize the anneal temperature of such devices (e.g., to ensure optimal activation temperatures for n-type and p-type dopants during anneals). Selectively controlling the temperature changes in different devices during a rapid thermal anneal can be accomplished by selectively varying the isolation material thickness in different sections of a shallow trench isolation structures (e.g., in sections that are adjacent to different devices). Alternatively, it can be accomplished by selectively varying the pattern of fill structures in different sections of a semiconductor wafer so that predetermined amounts of shallow trench isolation regions in the different sections are exposed.

More particularly, one embodiment the semiconductor structure comprises a substrate, an insulator layer on the substrate, and both a first film and a second film above the insulator layer. Specifically, the first film comprises a first material (e.g., a single crystalline semiconductor material such as silicon). Additionally, devices (e.g., at least one first device and at least one second device) can be formed in this first film. The second film comprises a second material that is also above the insulator layer such that it is positioned laterally adjacent to the first film. The second material can comprise an isolation material (e.g., an oxide and/or a nitride material). For example, the second material can comprise the same dielectric material as the insulator layer.

The second film can further comprise a first section with a first thickness adjacent to a first device in the first film. The second film can also comprise a second section with a second thickness adjacent to a second device in the first film. The second thickness of the second section can be different from the first thickness of the first section. These first and second thicknesses can be predetermined to control reflectance and absorption characteristics in the area of the first film that contains the first device(s) and in the area of the first film that contains the second device(s), respectively. Specifically, the first and second thicknesses are predetermined so that the first device(s) and the second device(s) can achieve predetermined maximum temperatures during a single rapid thermal anneal process so that optimal dopant activation temperatures are achieved and/or so that the first device(s) and the second device(s) will exhibit predetermined performance characteristics following a rapid thermal anneal.

Also disclosed is an embodiment of a method of forming the semiconductor structure, described above. This embodiment comprises providing a substrate and forming an insulator layer on the substrate. A first film is formed on the insulator layer. This first film can comprise a first material, for example, a single crystalline semiconductor material such as silicon. Thus, the first film can correspond to a device region of the semiconductor structure. A second film, comprising a second material that is different from the first material, is also formed on the insulator layer adjacent to the first film. The second material can comprise an isolation material (e.g., an oxide and/or nitride material) and can, for example, comprise the same dielectric material as the insulator layer (e.g., silicon dioxide). Thus, the second film can correspond to an isolation region (e.g., a shallow trench isolation region) of the semiconductor structure. The second film is specifically formed with a first section having a first thickness and a second section having a second thickness that is different from the first thickness.

Prior to formation of the semiconductor structure, the desired first and second thicknesses of the first and second sections, respectively, of the second film (i.e., a shallow trench isolation region) are predetermined so as to selectively control reflectance and absorption characteristics in areas of the first film adjacent to the different sections of the second film. Specifically, the first and second thicknesses are predetermined so that subsequently formed first device(s) in the first film adjacent to the first section of the second film and subsequently formed second device(s) in the first film adjacent to the second section of the second film will be able to achieve predetermined maximum temperatures during a single rapid thermal anneal process so that optimal dopant activation temperatures are achieved and/or so that the devices will exhibit predetermined performance characteristics following the rapid thermal anneal.

To form the second film with different thicknesses in different section, the second material is planarized after it is deposited. Then, the first film, the second film or neither is etched back as necessary so that the desired first thickness is achieved. Then, a photoresist layer can be deposited over the structure and lithographically patterned to expose a portion of the second film. Next, the exposed portion of the second film can be etched back to the desired second thickness.

Following formation of the first and second films above the insulator layer, at least one first device can be formed in the first film adjacent to the first section of the second film and at least one second device can be formed in the first film adjacent to the second section of the second film.

In another embodiment the semiconductor structure comprises a first section and a second section. The first section comprises at least one first device and a first isolation region adjacent to the first device(s). The second section similarly comprises at least one second device and a second isolation region adjacent to the second device(s). Both sections also comprise a plurality of fill structures that are positioned in predetermined patterns so that only predetermined amounts of the isolation material of the isolation regions are exposed. These fill structures can comprise, for example, single crystalline semiconductor structures positioned laterally adjacent to the first and second isolation regions, polycrystalline semiconductor structures positioned above the first and second isolation regions, and/or dielectric structures positioned above the first and second isolation regions. The first amount of the isolation material of the first isolation region that is exposed in the first section and the second amount of the isolation material of the second isolation region that is exposed in the second section are each predetermined so that the first device and the second device achieve predetermined maximum temperatures during a rapid thermal anneal process in order to achieve optimal dopant activation temperatures (e.g., different predetermined dopant activation temperatures) and/or so that the first device and the second device will exhibit predetermined performance characteristics following the rapid thermal anneal (e.g., the same or different predetermined performance characteristics).

Also disclosed is an embodiment of a method of forming the semiconductor structure, described above. This embodiment comprises providing a substrate (e.g., a semiconductor wafer) and forming on the substrate a first section with at least one first device and a first isolation region adjacent to the first device(s) and a second section with at least one second device and a second isolation region adjacent to the second device(s).

Fill structures are also formed in the first and second sections. Specifically, the fill structures can be formed in each of the sections and can be formed in predetermined patterns so that a first amount of the isolation material in the first isolation region of the first section will be exposed and similarly so that a second amount of the isolation material in the second isolation region of the second section will be exposed. The first and second amounts of exposed isolation material in the first and second sections, respectively, are predetermined so that the first and second devices will each achieve predetermined maximum temperatures during a rapid thermal anneal so that the devices are subjected to optimal dopant activation temperatures during a rapid thermal anneal and/or so that the first and second devices exhibit predetermined performance characteristics following the rapid thermal anneal (e.g., the same or different threshold voltages).

This method embodiment, as described above, illustrates the fill structures being formed such that the first and second patterns are achieved in the first and second sections, respectively. However, alternatively, a generic wafer with a surplus of fill structures can be formed. Then specific fill structures can be selectively removed from different sections of the wafer in order to achieve the predetermined patterns, described above. If a generic wafer with a surplus of fill structures is used, but not enough fill structures are present in a particular section, additional fill structures can also be formed, as necessary, in order to achieve the predetermined patterns.

Fill structures can be formed by forming single crystalline semiconductor structures so that they are positioned laterally adjacent to the first and second isolation regions in the first and second sections, respectively. Fill structures can also be formed by forming polycrystalline semiconductor structures above the first and second isolation regions in the first and second sections, respectively. Finally, fill structures can also be formed by forming dielectric structures above the first and second isolation regions in the first and second sections, respectively.

These and other aspects of the embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments of the invention and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments of the invention without departing from the spirit thereof, and the embodiments of the invention include all such modifications.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the invention will be better understood from the following detailed description with reference to the drawings, in which:

FIG. 1 is a schematic diagram illustrating an embodiment of a semiconductor structure of the invention;

FIG. 2 is a flow diagram illustrating an embodiment of a method of forming the semiconductor structure of FIG. 1;

FIG. 3 is a schematic diagram illustrating a partially completed semiconductor structure of FIG. 1;

FIG. 4 is a schematic diagram illustrating a partially completed semiconductor structure of FIG. 1;

FIG. 5 is a schematic diagram illustrating a partially completed semiconductor structure of FIG. 1;

FIG. 6 is a schematic diagram illustrating a partially completed semiconductor structure of FIG. 1;

FIG. 7 is a schematic diagram illustrating another embodiment of a semiconductor structure of the invention;

FIG. 8 is a schematic diagram illustrating an A-A′ cross-section view of the semiconductor structure of FIG. 7; and

FIG. 9 is a schematic diagram illustrating an embodiment of a method of forming the semiconductor structure of FIG. 7.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The embodiments of the invention and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments of the invention. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments of the invention may be practiced and to further enable those of skill in the art to practice the embodiments of the invention. Accordingly, the examples should not be construed as limiting the scope of the embodiments of the invention.

As mentioned above, variations in reflectance and absorption characteristics can be caused by a variety of different factors including, different materials, the patterns of those materials in different regions of a wafer and the thicknesses of those materials in different regions of the wafer. For example, dielectric materials (e.g., silicon dioxide (SiO₂)) in shallow trench isolation structures have different reflectance and absorption characteristics than semiconductor materials (e.g., silicon or silicon germanium) incorporated into devices. These different reflectance characteristics can result in non-uniform temperature changes across the wafer during a rapid thermal anneal (RTA) process. Non-uniform temperature changes can cause variations in dopant activation, damage repair, etc. across the wafer and can, thereby, cause variations in threshold voltages, sheet resistances, drive currents, leakage currents, etc. between devices on different regions of the wafer. Thus, non-uniform temperature changes can cause significant, location-dependent, variations in device performance. It would be advantageous over the prior art to provide a wafer structure with pre-determined variations in reflectance and absorption characteristics in order to control temperature changes during a rapid thermal anneal and, thereby, to selectively control variations in device performance. For example, it would be advantageous over the prior art to selectively vary the reflectance and absorption characteristics in different regions of a wafer in order to either selectively vary the performance of devices in different regions on the same wafer (e.g., to form devices with different threshold voltages (Vt) in different regions on the same wafer) and/or to selectively vary the anneal temperature of such devices (e.g., to ensure optimal activation temperatures for n-type and p-type dopants during anneals).

In view of the foregoing, disclosed herein are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal (i.e., to control the maximum temperature achieved in different regions or at different devices during a rapid thermal anneal) and, thereby, to selectively control variations in device performance (e.g., to form devices with the same or different threshold voltages (Vt) in different regions on the same wafer) and/or to selectively optimize the anneal temperature of such devices (e.g., to ensure optimal activation temperatures for n-type and p-type dopants during anneals). Selectively controlling the temperature changes in different devices during a rapid thermal anneal can be accomplished by selectively varying the isolation material thickness in different sections of a shallow trench isolation structures (e.g., in sections that are adjacent to different devices). Alternatively, it can be accomplished by selectively varying the pattern of fill structures in different sections of a semiconductor wafer so that predetermined amounts of shallow trench isolation regions in the different sections are exposed.

More particularly, referring to FIG. 1, one embodiment the semiconductor structure 100 comprises a substrate 150 (e.g., a semiconductor wafer), an insulator layer 130 on the substrate 150, and both a first film 110 and a second film 120 above the insulator layer 130. Specifically, the first film 110 comprises a first material. The first material can comprise a semiconductor (e.g., a single crystalline semiconductor material such as silicon). Additionally, devices (e.g., at least one first device 111 and at least one second device 112) can be formed in this first film 110. Thus, the first film 110 can correspond to a device region of the semiconductor structure 100. The second film 120 comprises a second material that is also above the insulator layer 130 such that it is positioned laterally adjacent to the first film 110. The second material can comprise an isolation material (e.g., an oxide and/or a nitride material). For example, the second material can comprise the same dielectric material as the insulator layer 130 (e.g., silicon dioxide). Thus, the second film 120 can correspond to an isolation region (e.g., a shallow trench isolation region) of the semiconductor structure 100.

The second film 120 can further comprise a first section 121 adjacent to the first device(s) 111 in the first film 110. This first section 121 can have a predetermined first thickness 141. The second film 120 can also comprise a second section 122 adjacent to the second device(s) 112 in the first film 110. This second section 122 can have a predetermined second thickness 142 that is different from the first thickness 141 of the first section 121. These first and second thicknesses 141, 142 can be predetermined in order to control reflectance and absorption characteristics in an area of the first film 110 that contains the first device(s) 111 and that is adjacent to the first section 121 of the second film 120 and also to control the reflectance and absorption characteristics in an area of the first film 110 that contains the second device(s) 112 and that is adjacent to the second section 122 of the second film 120. Although FIG. 1 illustrates both the first thickness 141 of the first section 121 of the second film 120 and the second thicknesses 142 of the second section 122 of the second film 120 as being less than the thickness of the first film 110, it is anticipated that either one or both of these thicknesses 141, 142 may alternatively be the same or greater than that of the first film 110.

More specifically, the first and second thicknesses 141, 142 are predetermined so that the first device(s) 111 and the second device(s) 112 can achieve predetermined maximum temperatures during a rapid thermal anneal process. The maximum temperature achievable at the different devices can be predetermined in order to ensure that optimal dopant activation temperatures are achieved. For example, it is well-known in the art that different dopants (e.g., n-type dopants such as phosphorous (P), antimony (Sb), and arsenic (As) and p-type dopants such as boron (B)) have different activation temperatures. Therefore, to optimize the dopant activation, the thicknesses 141, 142 of different sections 121, 122 of STI 120 adjacent to devices 111, 112 with different dopants can be selectively adjusted. Selectively varying the STI thickness in different sections can be used to selectively vary the anneal temperatures of adjacent devices and, thus, to vary the temperature at which the dopants in those device are activated.

Alternatively or additionally, he maximum temperature achievable at the different devices can be predetermined so that the first and second devices will exhibit predetermined performance characteristics following a rapid thermal anneal. For example, it is well known that different anneal temperatures can cause devices to exhibit different threshold voltages, sheet resistances, drive currents, leakage currents, etc. Therefore, in order to selectively control the performance characteristics of different devices (e.g., the threshold voltages, sheet resistances, drive currents, leakage currents, etc. of different devices), the thicknesses 141, 142 of different sections 121, 122 of STI 120 adjacent to those different devices 111, 112 can be selectively adjusted. By selectively varying the thickness 142 of a section 122 of STI 120 adjacent to a given device 112 the performance of that device 112 can be selectively varied as compared to the performance of a different device 111 adjacent to a different section 121 of STI 120 with a different thickness 141.

Referring to FIG. 2, also disclosed is an embodiment of a method of forming the semiconductor structure 100 of FIG. 1, described above. This embodiment comprises providing a substrate 150, e.g., a semiconductor wafer (202) and forming an insulator layer 130 on the substrate 150 (204, see FIG. 3). A first film 110 is formed on the insulator layer 130 (206). This first film 110 can comprise a first material, for example, a single crystalline semiconductor material such as silicon (Si). Thus, the first film 110 can correspond to a device region of the semiconductor structure 100 of FIG. 1. A second film 120, comprising a second material that is different from the first material, is also formed on the insulator layer 130 adjacent to the first film 110 (208, see FIGS. 4-5). The second material can comprise an isolation material (e.g., an oxide and/or nitride material) and can, for example, comprise the same dielectric material as the insulator layer 130 (e.g., silicon dioxide). Thus, the second film 120 can correspond to an isolation region (e.g., a shallow trench isolation region) of the semiconductor structure 100 of FIG. 1. As illustrated in FIG. 1, the second film 120 is specifically formed with a first section 121 having a first thickness 141 and a second section 122 having a second thickness 142 that is different from the first thickness 141 (210).

Forming the adjacent first and second films above the insulator layer can be accomplished at process 206-208, for example, by depositing the first material on the insulator layer 130 (see FIG. 3). A trench 165 is formed (e.g., lithographically patterned and etched) through the first material 110 to expose a portion of the insulator layer 130 (see FIG. 4). Next, the second material is deposited and planarized, filling the trench 165 such that the second film 120 is formed on the insulator layer 130 and is positioned laterally adjacent to the first film 110 (see FIG. 5).

Prior to formation of the semiconductor structure 100, the desired first and second thicknesses 141, 142 of the first and second sections 121, 122, respectively, of the second film 120 (i.e., a shallow trench isolation region) are predetermined so as to selectively control the reflectance and absorption characteristics in an area of the first film 110 that will contain first device(s) 111 and that is adjacent to the first section 121 of the STI 120 and to also selectively control reflectance and absorption characteristics in an area of the first film 110 that will contain second device(s) 112 and that is adjacent to the second section 122 of the STI 120. Specifically, the first and second thicknesses 141, 142 are predetermined so that subsequently formed first device(s) 111 in the first film 110 adjacent to the first section 121 of the second film 120 and subsequently formed second device(s) 112 in the first film 110 adjacent to the second section 122 of the second film 120 will be able to achieve a predetermined maximum temperature during a rapid thermal anneal. This maximum temperature can be predetermined so that optimal dopant activation temperatures are achieved and/or so that the devices will exhibit predetermined performance characteristics following such a rapid thermal anneal. See discussions below regarding device formation at process 212 and RTA at process 214.

At process 210, the thickness of different sections 121, 122 of the second film 120 deposited into the trench 165 (see FIG. 3) are selectively adjusted in order to form the second film 120 with the first section 121 having the first thickness 141 and the second section 122 having the second thickness 142. More specifically, after depositing the second material into the trench 165, the film 120 can be planarized and the first film 110, the second film 120 or neither can be selectively etched back, as necessary, to achieve the desired first thickness 141. Then, a photoresist layer 161 can be deposited over the structure and lithographically patterned to expose a portion 162 of the second film 120. Next, the exposed portion 162 of the second film 120 can be etched back to the desired second thickness 142 (see FIG. 6). Although FIG. 6 illustrates both the first thickness 141 of the first section 121 of the second film 120 and the second thicknesses 142 of the second section 122 of the second film 120 as being less than the thickness of the first film 110, it is anticipated and those skilled in the art will recognize that, due to the method steps described above, either one or both of these thicknesses 141, 142 may be the same or greater than that of the first film 110.

Following formation of the first and second films 110, 120 above the insulator layer 130 at processes 204-210, described above, at least one first device 111 can be formed in the first film 110 adjacent to the first section 121 of the second film 120 and at least one second device 112 can be formed in the first film 110 adjacent to the second section 122 of the second film 120 (212).

Following device formation at process 212, a conventional rapid thermal anneal (RTA) process can be performed (214). The different predetermined thicknesses 141, 142 of the STI 120 are used to selectively control the reflectance and absorption characteristics exhibited across the wafer during this RTA process and, thus, the maximum achievable anneal temperature for a given single rapid thermal anneal process (216) (e.g., so that predetermined dopant activation temperatures can be achieved in the different devices 111, 112 during the anneal (217) and/or so that predetermined performance characteristics will be exhibited by the devices 111, 112 after the anneal (218).

While the structure 100 and associated method embodiments described above refer to the STI 120 as having only two sections with different thicknesses, it is anticipated that the STI 120 may be formed with many sections having different thicknesses so as to control the reflectance and absorption characteristics in many different areas of the device region 110.

Referring to FIGS. 7 and 8 in combination, another embodiment the semiconductor structure 700 comprises a substrate 750 and first and second sections 710, 720 adjacent to each other above the substrate 750. The first section 710 comprises at least one first device 711 and a first isolation region 712 (e.g., a shallow trench isolation region (STI) comprising an isolation material (e.g., silicon dioxide)) adjacent to the first device(s) 711. The second section 720 similarly comprises at least one second device 721 and a second isolation region 722 (e.g., a shallow trench isolation region (STI) comprising the same isolation material as the first isolation region 712) adjacent to the second device(s) 721.

Both sections 710, 720 also comprise a plurality of fill structures 751-753 that are positioned in predetermined patterns (i.e., a first pattern in the first section and a second pattern in the second section) both horizontally and vertically adjacent to their respective isolation regions 712, 722 so that only predetermined amounts of the isolation material of the isolation regions 712, 722 are exposed. The predetermined patterns refer to the types, quantities, densities and locations of the fill structures 751-753 within the sections 710, 720. These fill structures can comprise, for example, single crystalline semiconductor structures (e.g., silicon structures, such as dummy device structures 751) positioned laterally adjacent to the first and second isolation regions 712, 722. They can comprise polycrystalline semiconductor structures (e.g., polysilicon structures, such as dummy polysilicon gate structures 752) positioned above the first and second isolation regions 712, 722, and/or above the dummy devices 751. Finally, they can comprise dielectric structures (e.g., oxide structures, nitride structures, oxide-nitride stacks, etc.) positioned above the first and second isolation regions 712, 722, above the dummy devices 751 and/or above the dummy gate structures 752.

The first pattern of the fill structures 751-753 in the first section 710 can be predetermined so that a predetermined first amount of the isolation material of the first isolation region 712 is exposed. Similarly, the second pattern of the fill structures 751-753 in the second section 720 can be predetermined so that a predetermined second amount of the isolation material of the second isolation region 722 is exposed. For example, as illustrated in FIG. 7, the pattern of fill structures 751-752 in the first section 710 exposes significantly more of the isolation material in the isolation region, than does the pattern of fill structures 751-753 in the second section 720. Selectively varying the fill structure patterns in the different section 710, 720 will vary the amount of STI 712, 722 exposed in each section and thus the reflectance and absorption characteristics of the different sections 710, 720. This in turn will vary the anneal temperatures experienced by the devices 711, 721 in those sections. Those skilled in the will recognize that a section 710 with a greater amount of exposed STI material will reflect more heat during a rapid thermal anneal and, thus, may not reach the same temperature during an RTA than a different section 720 with less exposed STI material. Therefore, by varying the amount of STI material exposed in the different sections, dopant activation temperatures can be optimized for devices 711, 721 in the different sections 710, 720 and/or desired performance characteristics can be achieved for devices 711, 721 in the different sections 710, 720.

Specifically, the first amount of the isolation material of the first isolation region 712 that is exposed in the section 710 and the second amount of the isolation material of the second isolation region 722 that is exposed in the second section 720 can each be predetermined so that the first device(s) 711 and the second device(s) 721 can achieve predetermined maximum temperatures in response to a given single rapid thermal anneal process. For example, it is well-known in the art that different dopants (e.g., n-type dopants such as phosphorous (P), antimony (Sb), and arsenic (As) and p-type dopants such as boron (B)) have different activation temperatures. Therefore, to optimize the dopant activation, the fill structure patterns in the different sections 710, 720 containing the devices 711, 721, respectively, can be selectively varied.

Alternatively or additionally, the different patterns can be predetermined so that the first device(s) 711 and the second device(s) 721 will exhibit predetermined performance characteristics following a rapid thermal anneal. For example, it is well known that different anneal temperatures can cause devices to exhibit different threshold voltages, sheet resistances, drive currents, leakage currents, etc. Therefore, in order to selectively control the performance characteristics (e.g., the threshold voltages, sheet resistances, drive currents, leakage currents, etc. of different devices) of different devices 711, 721, the fill structure patterns in the different sections 710, 720 that contain the devices can be selectively varied.

Referring to FIG. 9 in combination with FIGS. 7-8, also disclosed is an embodiment of a method of forming the semiconductor structure 700, described above. This embodiment comprises providing a substrate 750 (e.g., a semiconductor wafer) (902) and forming an isolation layer 730 on the substrate 750. Then, device and isolation regions are formed above the isolation layer 730 (904-907). Particularly, a first section 710 is formed with at least one first device 711 and a first isolation region 712 adjacent to the first device(s) 711. A second section 720 is also formed with at least one second device 721 and a second isolation region 722 adjacent to the second device(s) 721.

Fill structures 751-753 are also formed in the first and second sections 710, 720 horizontally and vertically adjacent to the first and second isolation regions 712, 722. Specifically, the fill structures 751-753 can be formed in each of the sections 710, 720 and can be formed in predetermined patterns (i.e., a first pattern in the first section 710 and a second pattern in the second section 720) in order to selectively control the reflectance and absorption characteristics of the sections 710, 720. These predetermined patterns refer to the types, quantities, densities and locations of the fill structures 751-753 within the sections 710, 720 (910)

Specifically, the first and second patterns can be predetermined so that a predetermined first amount of the isolation material in the first isolation region 712 of the first section 710 will be exposed (905) and similarly so that a predetermined second amount of the isolation material in the second isolation region 722 of the second section 720 will be exposed (907). The first and second amounts of exposed isolation material in the first and second sections 710, 720, respectively, can be predetermined so that the first and second devices 711, 721 will achieve different maximum anneal temperatures during a given single anneal process (908) (e.g., in order to achieve optimal dopant activation temperatures during the RTA (911) and/or so that the first and second devices 711, 721 will exhibit the same or different predetermined performance characteristics, such as different threshold voltages, following the RTA (912)).

This embodiment of the method, as described above, illustrates the fill structures 751-753 being formed such that the first and second patterns are achieved in the first and second sections 710, 720, respectively. However, alternatively, a generic wafer can be formed with a surplus of fill structures throughout the wafer. Then, specific fill structures can be selectively removed from different sections of the wafer (i.e., from first and second sections 710, 720) in order to achieve the predetermined first and second patterns at process 904-907. If a generic wafer with a surplus of fill structures 751-753 is used, but not enough fill structures are present in a particular section, additional fill structures can also be formed, as necessary, in order to achieve the predetermined first and second patterns.

Fill structures 751 can be formed by forming single crystalline semiconductor structures (e.g., silicon structures, such as dummy devices) so that they are positioned laterally adjacent to the first and second isolation regions 712, 722 in the first and second sections 710, 720, respectively. Fill structures 752 can also be formed by forming polycrystalline semiconductor structures (e.g., polysilicon structures, such as dummy polysilicon gate structures) above the first and second isolation regions 712, 722 and/or above the dummy devices 751 in the first and second sections 710, 720, respectively. Finally, fill structures 753 can also be formed by forming dielectric structures (e.g., by depositing and patterning an oxide layer, a nitride layer, an oxide-nitride stack, etc.) above the first and second isolation regions 712, 722, above the dummy devices 751 and/or above the dummy gate structure 752 in the first and second sections 710, 720, respectively. Thus, these fill structures 751-753 can be formed using conventional processing techniques for device formation, gate formation, nitride block formation, nitride stress memorization layer formation, etc.

While the structure 700 and associated method embodiments described above refer to the two different sections of the structure having different patterns of fill structures, it is anticipated that the structure 700 may be formed with many sections having different fill structure patterns so as to selectively control the reflectance and absorption characteristics within those sections.

Therefore, disclosed above are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal and, thereby, to selectively control variations in device performance (e.g., to form devices with different threshold voltages (Vt) in different regions on the same wafer) and/or to selectively optimize the anneal temperature of such devices (e.g., to ensure optimal activation temperatures for n-type and p-type dopants during anneals). Selectively controlling the temperature changes in different devices during a rapid thermal anneal can be accomplished by selectively varying the isolation material thickness in different sections of a shallow trench isolation structures (e.g., in sections that are adjacent to different devices). Alternatively, it can be accomplished by selectively varying the pattern of fill structures in different sections of a semiconductor wafer so that predetermined amounts of shallow trench isolation regions in the different sections are exposed.

Benefits that flow from this invention include reduced manufacturing cost by allowing for a plurality of device characteristics without adding process steps, and increased flexibility in circuit design, enabling reduced time to market. Furthermore, integrated circuits with lower operating and standby power, and higher speed are enabled by the art taught herein.

It should be noted that the inventors of the above embodiments have invented the following additional inventions related to the reflectance and absorption characteristics of wafers during rapid thermal anneals, each of which is being filed simultaneously herewith and is fully incorporated herein by reference: U.S. Pat. No. 7,679,166; (2) U.S. patent application Ser. No. 11/678,745, titled “Structure And Method For Device-Specific Fill For Improved Anneal Uniformity”, Attorney Docket No. BUR920060023US1; and (3) U.S. patent application Ser. No. 11/678,756, titled “Semiconductor Wafer Structure With Balanced Reflectance And Absorption Characteristics For Rapid Thermal Anneal Uniformity”, Attorney Docket No. BUR920060024US1.

The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, those skilled in the art will recognize that the embodiments of the invention can be practiced with modification within the spirit and scope of the appended claims. 

1. A method of forming a semiconductor structure comprising: providing a substrate; forming on a first section of said substrate at least one first device, a first isolation region adjacent to said first device, and fill structures adjacent to said first isolation region; and simultaneously forming on a second section of said substrate at least one second device, a second isolation region adjacent to said second device and said fill structures adjacent to said second isolation region, wherein a first pattern of said fill structures in said first section is such that a first amount of an isolation material in said first isolation region is exposed and wherein a second pattern of said fill structures in said second section is such that a second amount of said isolation material in said second isolation region is exposed.
 2. The method of claim 1, wherein said forming of said fill structures comprises at least one of the following: forming single crystalline semiconductor structures adjacent to said first isolation region and said second isolation region; forming polycrystalline semiconductor structures above said first isolation region and said second isolation region; and forming dielectric structures above said first isolation region and said second isolation region.
 3. The method of claim 2, wherein said forming of said single crystalline semiconductor structures comprises forming dummy devices in said first section and said second section
 4. The method of claim 2, wherein said forming of said polycrystalline semiconductor structures comprises forming dummy polysilicon gate structures in said first section and said second section
 5. The method of claim 2, wherein said forming of said dielectric structures comprises forming and patterning one of an oxide layer, a nitride layer and an oxide-nitride stack in said first section and said second section.
 6. The method of claim 1, further comprising predetermining said first amount of said isolation material exposed in said first section and said second amount of said isolation material exposed in said second section so that said first device and said second device achieve predetermined maximum temperatures during a single rapid thermal anneal.
 7. The method of claim 6, wherein said predetermined maximum temperatures are different optimal dopant activation temperatures for said first device and said second device.
 8. The method of claim 1, further comprising predetermining said first amount and said second amount so that said performance characteristics exhibited by said first device and said second device are different.
 9. A method of forming a semiconductor structure comprising: providing a substrate; forming on a first section of said substrate at least one first device, a first isolation region adjacent to said first device, and fill structures adjacent to said first isolation region; and simultaneously forming on a second section of said substrate at least one second device, a second isolation region adjacent to said second device and said fill structures adjacent to said second isolation region, wherein a first pattern of said fill structures in said first section is such that a first amount of an isolation material in said first isolation region is exposed and wherein a second pattern of said fill structures in said second section is such that a second amount of said isolation material in said second isolation region is exposed, and wherein said forming of said fill structures comprises forming a surplus of fill structures such that some of said fill structures can be selectively removed in order to form said first pattern and said second pattern.
 10. The method of claim 9, wherein said forming of said fill structures comprises at least one of the following: forming single crystalline semiconductor structures adjacent to said first isolation region and said second isolation region; forming polycrystalline semiconductor structures above said first isolation region and said second isolation region; and forming dielectric structures above said first isolation region and said second isolation region.
 11. The method of claim 9, wherein said forming of said single crystalline semiconductor structures comprises forming dummy devices in said first section and said second section
 12. The method of claim 9, wherein said forming of said polycrystalline semiconductor structures comprises forming dummy polysilicon gate structures in said first section and said second section
 13. The method of claim 9, wherein said forming of said dielectric structures comprises forming and patterning one of an oxide layer, a nitride layer and an oxide-nitride stack in said first section and said second section.
 14. The method of claim 9, further comprising predetermining said first amount of said isolation material exposed in said first section and said second amount of said isolation material exposed in said second section so that said first device and said second device achieve predetermined maximum temperatures during a single rapid thermal anneal.
 15. The method of claim 9, wherein said predetermined maximum temperatures are different optimal dopant activation temperatures for said first device and said second device.
 16. The method of claim 9, further comprising predetermining said first amount and said second amount so that said performance characteristics exhibited by said first device and said second device are different.
 17. A method of forming a semiconductor structure comprising: providing a substrate; forming on a first section of said substrate at least one first device, a first isolation region adjacent to said first device, and fill structures adjacent to said first isolation region; simultaneously forming on a second section of said substrate at least one second device, a second isolation region adjacent to said second device and said fill structures adjacent to said second isolation region, wherein a first pattern of said fill structures in said first section is such that a first amount of an isolation material in said first isolation region is exposed and wherein a second pattern of said fill structures in said second section is such that a second amount of said isolation material in said second isolation region is exposed; and predetermining said first amount of said isolation material exposed in said first section and said second amount of said isolation material exposed in said second section so that said first device and said second device exhibit predetermined performance characteristics following a rapid thermal anneal.
 18. The method of claim 17, wherein said forming of said fill structures comprises at least one of the following: forming single crystalline semiconductor structures adjacent to said first isolation region and said second isolation region; forming polycrystalline semiconductor structures above said first isolation region and said second isolation region; and forming dielectric structures above said first isolation region and said second isolation region.
 19. The method of claim 17, wherein said forming of said single crystalline semiconductor structures comprises forming dummy devices in said first section and said second section
 20. The method of claim 17, wherein said forming of said polycrystalline semiconductor structures comprises forming dummy polysilicon gate structures in said first section and said second section 